1. Field of the Invention
This invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a capacitor of a dynamic random access memory (DRAM).
2. Description of Related Art
Because microprocessors have become more and more powerful, and the structures of software applications and the performed algorithms have become more and more complicated, requirements on memory capacities have been increased accordingly. Currently, a memory cell of a DRAM normally consists of a transfer field effect transistor (TFET) and a storage capacitor. As shown in FIG. 1, a selected capacitor C of the array of capacitors on a semiconductor substrate is used to store a bit of binary data by charging and discharging the capacitor C. Normally, a binary 0 is stored in a capacitor if the capacitor is not charged, and a binary 1 is stored if the capacitor is charged. Within the capacitor C, dielectric 101 is filled into the space between the lower electrode (storage electrode) 100 and the upper electrode (cell electrode) 102 of the capacitor C to provide a required permittivity. The capacitor C is electrically connected to a bit line BL, so that data can be read or written through the bit line BL by charging or discharging the capacitor C. The task of charging or discharging the capacitor C is controlled and executed through a TFET, T, which is connected to the bit line BL on the drain, to the capacitor C on the source, and to the word line W1 on the gate. Signals are fed into the TFET T through the word line to control the connection between the capacitor C and the bit line BL.
In a conventional fabrication process of a DRAM of less than 1 megabyte in capacity, the capacitors are normally made in a two-dimension layout, a so-called planar-type capacitor. Since a conventional planar-type capacitor requires a relatively large planar area for storing charges, it is not suitable for serving in a highly integrated DRAM, such as a DRAM of larger than 4 megabytes in capacity. For the need of fabricating a highly integrated DRAM, a capacitor of a three-dimensional configuration, such as a stacked capacitor or a trench-type capacitor, is preferred.
A three-dimensional capacitor, such as a stacked capacitor or a trench-type capacitor, have been developed to store more charges without occupying a relatively large area on a semiconductor substrate as a conventional planar capacitor does. However, such a design still has certain difficulty to meet the requirement of a DRAM of higher integration and a higher capacity, such as 64 megabytes.
In order to resolve the foregoing problem, a so-called fin-type capacitor consisting of stacked and horizontally extended electrodes and dielectric has been introduced. By stacking several horizontally extended electrodes and dielectric, the total surface area of a fin-type capacitor is increased for storing more charges. More detailed description on the fabrication of a fin-type capacitor can be found in U.S. Pat. Nos. 5,071,783, 5,126,810, and 5,206,787. A research done by Ema ("3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs", International Electronic Devices Meeting, p.p. 592-595, December 1988) is also referential.
The foregoing problems can also be resolved by extending the electrode and the dielectric layer of a capacitor vertically to form a so-called cylindrical-type capacitor. The permittivity of the capacitor is also increased according to the enlarged surface area of the capacitor electrode. More detailed description on the fabrication of a fin-type capacitor can be found in U.S. Pat. No. 5,077,688, or a research paper of Wakamita's ("Novel Stacked Capacitor Cell for 64M DRAMs", 1989 Symposium on VLSI Technology Digest of Technical Papers, p.p. 69-70, 1989).
It is obvious that downsizing a memory cell is an inevitable tendency, as the integration of semiconductor devices is further increased. However, the permittivity of a downsized storage capacitor is accordingly decreased, that is, the capacitor stores less charges. That increases the possibility of the occurrence of soft errors due to the incident .alpha. ray. Hence, people skilled in this art are still looking for a efficient fabricating method and more reliable structure of a DRAM cell in order to downsize the DRAM cell, and in the meantime, retain the permittivity of a storage capacitor as well.